Stress engineering techniques have been widely applied to sub-130 nm and beyond technology nodes. The main consideration of using stress engineering in CMOS technique is that PMOS and NMOS respond differently to different types of stress. To be more specific, a compressive stress is applied to the channel region to improve the PMOS performance, and a tensile stress is applied to the channel region to improve the NMOS performance.
A popular method includes using a stress induced by cap layer. Forming silicon nitride using CVD is a common choice for forming the stress cap layer. The magnitude and type of the stress may be changed by adjusting deposition conditions such as temperature and frequency. The stress induced by cap layer may be selectively deposited by a standard photolithography/etching technique, for example, depositing a compressive stress thin film on PMOS only. A dual stress liner (DSL) may be applied to the PMOS and NMOS in the DSL process, wherein the standard photolithography/etching technique is employed to selectively deposit a tensile stress silicon nitride thin film on the NMOS, and selectively deposit a compressive stress silicon nitride thin film on the PMOS. Specifically, the method comprises first depositing a SiN thin film of the tensile stress on both the NMOS and PMOS, then masking the NMOS region with a photoresist layer and exposing the PMOS region, etching to remove the tensile stress SiN on the exposed PMOS region, and depositing again a SiN thin film of the compressive stress on PMOS, masking the PMOS region with a photoresist layer and exposing the NMOS region, etching to remove the tensile stress SiN on the exposed NMOS region, and removing the photoresist layer remaining on the PMOS region. This method requires a series of spin coating, photolithography and etching, resulting in complex processes and high cost. Besides, when the compressive stress SiN thin film is being deposited on PMOS, the change of such deposition parameters as high temperature and high pressure will affect the property of the tensile stress SiN thin film on the NMOS region. In addition to changing the magnitude of the stress, it is even possible that the type of stress might be changed, thus severely influencing the improvement of the carrier mobility of the NMOS channel region and degrading the device performance.
Another method is using a silicon-rich material, especially SiGe, to adjust the channel stress. This manufacturing method includes epitaxial growth of Si on a relaxed SiGe layer. Because the crystal lattice of the Si layer extends to match the larger lattice constant of the SiGe layer, a tensile stress is introduced into the Si layer. This method effectively avoids the problem resulted from the change in the magnitude and type of the stress of the SiN cap layer due to the change of process parameters, but different substrates such as SiGe and SiC are required for the PMOS and NMOS devices, respectively, thus being unable to be completely compatible with the existing single Si substrate process when manufacturing a CMOS. Instead, SiGe or SiC has to be grown on the Si substrate, which is a more complex process and the adjustment of the various parameters is pretty difficult.
To sum up, in the existing stressed MOSFET, the conventional method for providing a stress has a complex process, high cost and low reliability, and thus there is a need for a new CMOS device capable of effectively controlling the channel stress to improve the carrier mobility and thereby enhance the device performance and a method for manufacturing the same.